The present invention relates to a semiconductor apparatus in which a vertical NPN bipolar transistor, a vertical PNP bipolar transistor, or a CMOS transistor is integrated on a semiconductor substrate and to a method of manufacturing the same. It also relates to a method of manufacturing a semiconductor apparatus having a capacitor provided on a semiconductor substrate and used together with a bipolar transistor.
In recent years, there has been a demand for a high-density, high-speed semiconductor apparatus which consumes less power.
A representative of such conventional semiconductor apparatuses is an NPN bipolar transistor of walled-emitter type. The NPN bipolar transistor has a structure in which its emitter region is surrounded by an insulating film so that at least a part of the emitter region is in contact with its periphery. The structure not only enables the reduction of junction capacitance between its emitter and base and the miniaturization of the transistor due to the self-aligning formation of its emitter and base, but also fulfills the requirements of high speed, high density, and low power consumption imposed on the transistor. An example of the NPN bipolar transistor of walled-emitter type is disclosed in, e.g., Japanese Laid-Open Patent Publication No. 1-281769.
In an NPN bipolar transistor of such structure, however, since the impurity introduced into its base region by ion implantation is absorbed by the insulating film, a depletion layer is formed at the interface of the base region with the insulating film due to the lowering of impurity concentration. As a result, the N.sup.- -type emitter region and N.sup.- -type collector region are connected to each other via the depletion layer, resulting in the undesirable generation of a leakage current between the emitter region and collector region.
In a semiconductor apparatus having a PNP bipolar transistor on a semiconductor substrate, on the other hand, the impurity implanted in the collector region is absorbed by the insulating film at the interface of the P.sup.+ -type collector region with the insulating film, so that a depletion layer is formed at the interface of the collector region with the insulating film. In the depletion layer, there exist a large number of interfacial charges. Holes in the foregoing depletion layer diffuse into the collector region, so that the foregoing depletion layer is connected to the depletion layer between the collector region and base region. Consequently, the depletion layer containing a large number of interfacial charges, which will as a current source, is formed between the collector contact region and base region, so that the leakage current is disadvantageously generated between the collector contact region and base region.
In a semiconductor apparatus having an N-channel MOS transistor on a semiconductor substrate, on the other hand, the impurity introduced into the P-type region, positioned between the N-type source region and N-type drain region, is absorbed by the insulating film at the interface of the foregoing P-type region with the insulating film. As a result, a depletion layer is formed at the interface of the foregoing P-type region with the insulating film due to the lowering of impurity concentration. Consequently, the source region and drain region are connected to each other via the depletion layer, resulting in the undesirable generation of a leakage current between the source region and drain region.
Thus, the leakage currents are generated in the respective portions stated above of the conventional semiconductor apparatuses in which the vertical NPN bipolar transistor, vertical PNP bipolar transistor, and CMOS transistor are integrated on the semiconductor substrates, resulting in the lowering of the production yields of the transistors.
Below, there will be described a conventional method of manufacturing a semiconductor apparatus having a capacitor provided on a semiconductor substrate and used together with a bipolar transistor.
As shown in FIG. 50A, an N.sup.+ -type buried layer 202 and an N.sup.- -type epitaxial layer 203 are sequentially formed on a P-type semiconductor substrate 201. A thermal oxide film 204 is then formed on the N.sup.- -type epitaxial layer 203 by selective oxidation. Thereafter, an N.sup.+ -type diffusion layer 205, which will serve as a lower capacitor electrode, is formed using the thermal oxide film 204 as a mask.
Next, as shown in FIG. 50B, a CVD-SiO.sub.2 film 206 is formed, which is then subjected to etching using a first resist pattern 207 (photomask C1), thereby forming a capacitor insulating film formation region 208.
Next, as shown in FIG. 50C, a silicon nitride film 209, which will serve as a capacitor insulating film, is deposited thereon, followed by the formation of a second resist pattern 210 (photomask C2) on that portion of the silicon nitride film 209 which corresponds to the capacitor insulating film formation region 208 and to its vicinity. Thereafter, the silicon nitride film 209 is subjected to etching using the second resist pattern 210 as a mask.
Next, as shown in FIG. 50D, a third resist pattern 211 (photomask CW) is formed on the CVD-SiO.sub.2 film 206, so that the CVD-SiO.sub.2 film 206 is subjected to etching using the third resist pattern 211, thereby forming a contact region for the lower capacitor electrode.
Next, as shown in FIG. 50E, the third resist pattern 211 is removed and then an upper capacitor electrode 213 and the lower capacitor electrode 214 are formed by a normal wiring process using aluminium, thereby completing a capacitor.
However, the conventional method of manufacturing a semiconductor apparatus requires the process of forming a resist pattern to be performed three times (using the photomasks C1, C2, and CW) between the formation of the N.sup.+ -type diffusion layer 205 serving as the lower capacitor electrode and the formation of the contact region 212 for the lower capacitor electrode. Accordingly, the number of steps required for manufacturing the semiconductor apparatus and manufacturing cost are disadvantageously increased.
To reduce the number of steps in the conventional method of manufacturing a semiconductor apparatus, the step of etching away the silicon nitride film 209 using the second resist pattern 210 may be omitted. Below, such a manufacturing method for a semiconductor apparatus will be described.
As shown in FIG. 51A, after the deposition of the silicon nitride film 109 serving as the capacitor insulating film, the silicon nitride film 209 and CVD-SiO.sub.2 film 206 are etched away using the third resist pattern 211, thereby forming the contact region 212 for the lower capacitor electrode.
Next, the third resist pattern 211 is removed and then the process of forming aluminium wiring is performed. In general, the SiO.sub.2 film 206 is subjected to wet etching prior to the deposition of aluminium for the purpose of removing the natural oxide film of the contact region 212 for the lower capacitance electrode, so that the contact resistance between the aluminium and N.sup.+ -type diffusion layer 205 is reduced. In this case, however, side etching of the CVD-SiO.sub.2 film 206 occurs in the contact region 212 for the lower capacity electrode, as shown in FIG. 51B, resulting in the formation of an overhang portion 215.
Next, when the upper capacitor electrode 213 and lower capacitor electrode 214, each being made of aluminium, are deposited as shown in FIG. 51C, the step coverage with aluminium deteriorates significantly in the overhang portion 115, so that the amount of aluminium deposited in the overhang portion 115 becomes extremely small. Consequently, a broken portion 116 of the aluminium wire is generated in the overhang portion 115, as shown in FIG. 51C.